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This is the third installment in our CPU design series. In Part 1, we covered computer architecture and how a processor works at a high level. Part 2 explored the design and implementation of individual chip components. Now, in Part 3, we take things a step further to see how architectural and schematic designs are transformed into physical chips.
How do you transform a pile of sand into an advanced processor? Let’s find out.
Types of Transistors: nMOS and pMOS
As we discussed before, processors and all other digital logic circuits are built from transistors. A transistor is an electronically controlled switch that can be turned on or off by applying or removing voltage to the gate. We previously covered the two main types of transistors:
- nMOS devices, which allow current to flow when the gate is on.
- pMOS devices, which allow current to flow when the gate is off.
The base material of a processor, where transistors are embedded, is silicon. Silicon is classified as a semiconductor because it is neither a full conductor nor a full insulator – it falls somewhere in between.
Doping: Transforming Silicon into a Useful Circuit
To turn a wafer of silicon into a functioning circuit by adding transistors, engineers use a process called doping. This involves introducing carefully selected impurities into the silicon substrate to alter its conductivity.
The goal is to change the way electrons behave so that we can control them. Just like there are two types of transistors, there are also two corresponding types of doping.
The fabrication process of a wafer before the chips are packaged. Photo credit: Evan Lissoos
If we add a precisely controlled amount of electron donor elements like arsenic, antimony, or phosphorus, we can create an n-type region. Since the silicon area where these elements were applied now has an excess of electrons, it will become negatively charged. This is where the name n-type and the “n” in nMOS comes from.
By adding electron acceptor elements like boron, indium, or gallium to the silicon, we can create a p-type region which is positively charged. This is where the “p” in p-type and pMOS come from. The specific processes to add these impurities to the silicon are known as Ion Implantation and Diffusion and they are bit beyond the scope of this article.
Now that we can control the electrical conductivity of certain regions of our silicon, we can combine the properties of multiple regions to create transistors.
The Role of Transistors
The transistors used in integrated circuits, known as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), have four connections. The current we are controlling flows through the Source and Drain. In an n-channel device it typically goes in the drain and out the source while in an p-channel device, it typically flows in the source and out the drain.
The Gate is the switch used to turn the transistor on and off. Finally, the Body of the device isn’t relevant to processor so we won’t discuss it here.
The physical structure of an inverter in silicon. Each colored region has different conductivity properties. Note how the different silicon components correspond to the schematic on the right
The technical details of how transistors work and how different regions interact are complex enough to fill a graduate-level course, so we’ll focus on the basics.
A helpful analogy for how they work is a drawbridge over a river. The cars, electrons in our transistor, would like to flow from one side of the river to the other, the source and drain of our transistor. Using an nMOS device as an example, when the gate is not charged, the drawbridge is up, the electrons can’t flow across the channel. When we lower the drawbridge, we form a road over the river and the cars can move freely. The same thing happens in a transistor. Charging the gate forms a channel between the source and drain allowing current to flow.
Photolithography: Printing Circuit Patterns on Silicon
To precisely control where the different p and n regions of the silicon are, manufacturers like Intel and TSMC use a process called photolithography. This is an extremely complex, multi-step process, and companies spend billions of dollars perfecting it to build smaller, faster, and more energy-efficient transistors. Imagine a super-precise printer used to draw the patterns for each region onto the silicon.
As transistor sizes have shrunk, traditional deep ultraviolet (DUV) lithography has reached its limits. To continue scaling, the industry has adopted Extreme Ultraviolet (EUV) lithography, which uses shorter wavelengths of light (~13.5 nm) to create finer patterns with higher precision. EUV allows for more densely packed transistors and reduces the number of masking steps needed, making fabrication more efficient.
The process of building transistors into a chip starts with a pure silicon wafer, which is heated in a furnace to grow a thin layer of silicon dioxide on top. A light-sensitive photoresist polymer is then applied over the silicon dioxide. By shining light at specific wavelengths onto the photoresist – now often using EUV for the most advanced nodes – we can strip the photoresist in the areas we want to dope. This is the lithography step, similar to how printers apply ink to certain areas of a page, just at a much smaller scale.
The wafer is then etched with hydrofluoric acid to dissolve the silicon dioxide where the photoresist was removed. The remaining photoresist is stripped away, leaving behind just the oxide layer beneath. The doping ions can now be applied to the wafer, selectively implanting themselves only in the exposed regions.
This process of masking, imaging, and doping is repeated dozens of times to slowly build up each feature level in a semiconductor. Once the base silicon level is done, metal connections will be fabricated on top to connect the different transistors together. We’ll cover more about these connections and metal layers in a bit.
The Fabrication Process
Of course, chip makers don’t just do this process of making transistors one at a time. When a new chip is designed, they will generate masks for each step in the fabrication process. These masks will contain the locations of each element of the billions of transistors on a chip. Multiple chips are grouped together and fabricated at once on a single die.
Once a wafer is fabricated, the individual dies are sliced up and packaged. Depending on the size of a chip, each wafer may fit hundreds or more chips. Typically, the more powerful the chip being produced, the larger the die will be and the fewer chips the manufacturer will be able to get from each wafer.
It’s easy to think that we should just make massive chips that are super powerful and with hundreds of cores, but that isn’t possible. Currently, the single biggest factor preventing us from making bigger and bigger chips are defects in the manufacturing process. Modern chips have billions of transistors and if a single part of one is broken, the whole chip may need to be thrown away. As we increase the size of processors, the chance that a chip will be faulty increases.
Process Nodes and Manufacturing Transistors at Scale
The actual yields that companies get from their fabrication processes are closely held secrets, but anywhere from 70% to 90% is a good estimate. It is common for companies to over-engineer their chips with extra functionality since they know some parts won’t work. For example, Intel may design an 8-core chip but only sell it as a 6-core chip since they estimate that one or two cores may be broken. Chips with an unusually low number of defects are usually set aside to be sold at a higher price in a process known as binning.
One of the biggest marketing terms associated with chip fabrication is feature size or process node. For example, TSMC is now working towards a “2nm” process. However, for the past decade or so, the process node size has lost a true relation to any actual physical feature (such as gate length, metal pitch, or gate pitch) of transistors. Instead, it has become more of a cadence and marketing term used to refer to increasingly advanced fabrication technologies.
Just a few years ago, 7nm and 10nm were considered pioneering technologies. Today, Apple is already using 3nm for some of its SoCs, while Nvidia utilizes a 5nm process for its latest GPUs. But what do these numbers actually mean? Traditionally, the feature size referred to the minimum width between the drain and source of a transistor. As technology has advanced, transistors have continued to shrink, allowing for higher transistor density, improved performance, and greater energy efficiency.
When examining these process nodes, it’s important to note that different companies define their sizes differently. As a result, a 5nm process from one manufacturer may produce transistors that are similar in size to a 7nm process from another. Additionally, not all transistors within the same fabrication process are the same size. Designers may intentionally create some transistors larger than others, depending on specific performance requirements.
Automated Design and Optimization
For a given design process, smaller transistors switch faster because they require less time to charge and discharge the gate. However, they can only drive a limited number of outputs due to their reduced current-handling capacity. If a particular circuit needs to drive a high-power load, such as an output pin, its transistors must be significantly larger. In some cases, output transistors can be orders of magnitude larger than the internal logic transistors.
A die shot of an AMD Zen processor. Several billion transistors make up this design.
Designing and building the transistors is only half of the chip though. We need to build wires to connect everything according to the schematic. These connections are made using metal layers above the transistors. Imagine a multi-level highway interchange with on-ramps, off-ramps, and different roads crossing each other. That’s exactly what is going on inside a chip, albeit on a much smaller scale. Different processes will have different numbers of metal interconnect layers above the transistors.
As transistors get smaller, more metal layers are needed to be able to route all the signals. TSMC’s 5nm process has a reported 15 metal layers. Imagine a 15-level vertical highway interchange and that will give you an understanding for just how complex the routing is inside a chip.
The microscope image below shows the lattice formed by seven metal layers. Each layer is flat and as they go higher, the layers get bigger to help reduce resistance. In between each layer are small metal cylinders known as vias that are used to jump up to a higher layer. Each layer typically alternates in direction from the one below it to help reduce unwanted capacitances. The odd metal layers may be used to make horizontal connections while the even layers may be used to make vertical connections.
As you can imagine, all these signals and metal layers get incredibly difficult to manage very quickly. To help solve this issue, computer programs are used to automatically place and route the transistors. Depending on how advanced the design is, programs can even translate functions in high-level C code down to the physical locations of every wire and transistor. Typically, chip makers will let computers generate most of the design automatically and then they will go through and optimize certain critical sections by hand.
The Complexity of Modern CPU Design
When companies want to build a new chip, they will start their design with standard cells that the fabrication company provides. For example, Intel or TSMC will provide designers with basic parts like logic gates or memory cells. The designers can then combine these standard cells into whatever chip they want to build. They will then send the foundry, the place where the raw silicon is turned into functioning chips, the layouts of the chip’s transistors and metal layers. These layouts are turned into masks which are used in the fabrication process we covered above. Next we’ll see what this design process might look like for an extremely basic chip.
First we see the layout for an inverter which is a standard cell. The slashed green rectangle at the top is the pMOS transistor and the transparent green rectangle at the bottom is the nMOS transistor. The vertical red wire is the polysilicon gate, the blue areas are metal 1, and the purple areas are metal 2. The input A comes in on the left and the output Y goes out on the right. The power and ground connections are made at the top and bottom on metal 2.
Combining several gates, here we have a basic 1-bit arithmetic unit. This design can add, subtract, and perform logical operations on two 1-bit inputs. The slashed blue wires that go vertically are metal 3 layers. The slightly larger squares on the ends of the wires are vias that connect two layers.
Finally, by combining many standard cells and approximately 2,000 transistors, we can create a basic 4-bit processor with 8 bytes of RAM on four metal layers.
Even at this small scale, the complexity is evident. Now, imagine the challenge of designing a 64-bit CPU with megabytes of cache, multiple cores, and over 20 pipeline stages. Given that today’s high-performance CPUs contain upwards of 5 to 10 billion transistors and a dozen or more metal layers, it’s no exaggeration to say that they are millions of times more complex than this basic design.
This should give you a better appreciation for why modern CPUs are expensive and why it takes AMD and Intel so long between product releases. The development cycle for a new chip typically takes 3 to 5 years, from initial design to market availability. Some advancements, such as AI-driven chip design (as mentioned in Part 2) and chiplet architectures, may be accelerating development timelines slightly. However, this still means that today’s fastest chips were designed several years ago, and we won’t see chips with today’s state of the art fabrication technology until years down the line.
With that, our deep dive into processor fabrication comes to an end.
In the fourth and final installment of this series, we’ll shift our focus away from the physical aspects of chip manufacturing and explore current industry trends. What are researchers working on now to make the next generation of computers even faster?
In this installment, we explored how transistors function at a fundamental level, how their individual components are fabricated in silicon, and how they are connected to form useful circuits and chips.
Masthead credit: Macro photo
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