Arm and RISC-V: Can there only be one?

In almost every discussion about RISC-V’s position in the ecosystem, the instruction set architecture (ISA) is often seen as a direct competitor to Arm. Most people view the two ISAs as being engaged in a winner-take-all, zero-sum contest, where only one can prevail. However, we believe that, at least for the foreseeable future, the industry will witness a greater degree of mixing and matching. Both ISAs are likely to coexist side by side within increasingly heterogeneous chips.

Editor’s Note:
Guest author Jonathan Goldberg is the founder of D2D Advisory, a multi-functional consulting firm. Jonathan has developed growth strategies and alliances for companies in the mobile, networking, gaming, and software industries.

Admittedly, the entire history of technology is against us on this one. Over the past 40 years, we have seen a recurring pattern: software ecosystems tend to consolidate around a single platform. No one wants to write the same software twice, and not just write but design, test, and debug. So, developers have generally followed their own paths to maximize profits, which, over time, leads to the dominance of a single platform.

However, this old truism is not entirely accurate… ISAs are not exactly software.

Much of an ISA’s functionality lies in providing a common set of low-level language tools. These tools enable higher-level software to fully utilize the capabilities of the chip running each ISA. Therefore, some software tendencies still hold.

For user-level functionality (such as applications, infrastructure, and apps), a penalty remains for supporting multiple ISAs, as evidenced by Arm’s decade-long slog to enter the data center market. However, ISAs are rarely touched directly by this kind of software developer. Instead, ISAs are more crucial for chip designers – and they, too, are not keen on supporting multiple ISAs, as this requires multiple sets of tools and expertise. But this is a much smaller audience and a much more manageable problem. The cost-benefit equation plays out differently here. For a growing number of chip designers, the advantages of using multiple ISAs justify the cost of supporting both.

Chip designers usually have teams large enough to handle multiple layers of design expertise. Additionally, not all chip workloads are equal. In many cases, designing RISC-V cores alongside Arm cores can lead to superior solutions. RISC-V cores are not exactly free, but Arm cores tend to be more expensive, and the company appears intent on increasing those prices.

Arm cores are largely fixed in their capabilities, whereas RISC-V cores are marketed as being very ‘flexible’ (though not entirely, but close enough for our discussion). By mixing and matching the two systems, chip designers can find more optimal paths for their needs.

This is not just theory; we have seen it in practice. Apple’s A- and M-Series processors, as well as Google’s TPUs, appear to incorporate both Arm and RISC-V cores. This trend is evident in many other chips as well.

We recently spoke with a designer deeply involved in the IoT sector who we assumed used only RISC-V. He was quick to clarify, “I use both.” This all costs a bit more in terms of upfront costs and design team size, but the benefits clearly outweigh those costs in many cases.

Will this remain the case forever? Ask anyone on either side, and they are quick to say no. Highlander rules apply, there can be only one. However, in practice, we are not so certain. Chips are changing, becoming more diverse and heterogeneous, as designers search for ways to cope with the slowing of Moore’s Law. This has opened up the door to a rethinking of past rules. Therefore, we expect that for a long time to come, we will see both RISC-V and Arm sitting next to each other in many chips.